1. Field of the Invention
The present invention generally relates to efficient management of multiple instruction processors within a data processing environment and more particularly relates to scheduling of processing resources for the delivery of user selected video information to subscribing users.
2. Description of the Prior Art
It has been known for some time to employ multiple instruction processors within a single data processing system. Unless these instruction processors are dedicated to specific tasks (a very special purpose system architecture having limited utility), each of these instruction processors need to be assigned tasks from a common pool of tasks which much be accomplished. As the number of instruction processors becomes relatively large, the scheduling resources (e.g., scheduling script and common tasking data) can become so overloaded as to actually slow through-put of a system with the addition of instruction processors, because there is a problem in efficient scheduling of tasks.
Most modern instruction processors now employ some sort of cache memory to better match the internal speed within the instruction processor with the time it requires to access the instructions and data stored within memory. This generally takes the form of a hierarchy of cache memory subsystems wherein at least a portion of the cache memory is dedicated to an individual instruction processor. It is known in the art that the execution speed of a given instruction processor is maximized whenever the needed instructions and data are stored within the dedicated cache memory, generating a cache memory “hit”. Any cache memory “miss” (i.e., request for instruction(s) or data not currently found within cache memory) tends to slow execution as the required instruction(s) and/or data must be fetched from a larger and slower memory subsystem.
Thus, it is desirable to schedule like tasks to like instruction processors to improve execution efficiency by maximizing cache “hits”. If a given instruction processor only performs highly related tasks, virtually all execution will occur using the current cache memory contents without generating any cache “misses”. An “ideal” scheduler would always assign a given task (and highly related tasks) to the same instruction processor. This scheduling approach attempts to maximize instruction processor affinity. A problem with this approach is that the amount of logic to implement it tends to be unwieldy. Furthermore, restricting certain tasks to certain instruction processors produces difficulties with unbalanced loading of system resources. At any one instant, a limited number of instruction processor may be dedicated to execution of most of the total system load.
Therefore, it can be seen that employing the instruction processor affinity approach tends to maximized the execution efficiency of an individual instruction processor with a tendency to reduce over all system efficiency. However, more randomized scheduling, which improves equality of system loading, tends to reduce the execution efficiency of individual instruction processors.
An alternative approach is to use partitioned application systems. This solution employs two (or more) separate systems executing against the same database using a lock box to control access to the database. This allows more instruction processors to be allocated to the processing of a single application, albeit partitioned. This solution tends to be much more costly because a separate hardware component and dedicated software are required to maintain the Database integrity. The costs also are increased due to the additional processing overhead managing the system and database locks required to preserve the database integrity reducing the throughput of existing systems.